The present invention relates generally to digital communications systems, and more specifically to digital communications systems in which digital signals are asynchronously mapped/de-mapped from one clock domain to another.
Digital communications systems are known that can transport one or more digital signals, e.g., data frames, across multiple clock domains. A conventional digital communications system having such a capability includes a first communications network operating at a first clock rate connected to a second communications network operating at a second clock rate, in which the first clock signal is asynchronous to the second clock signal. The conventional digital communications system further includes a mechanism configured to compensate for the timing differences between the first and second clock signals when transporting the data frames between the first and second clock domains.
In the conventional digital communications system, the timing compensation mechanism typically includes a First-In First-Out (FIFO) buffer, in which digital information comprising incoming data frames can be written into the FIFO buffer at the first clock rate, and digital information comprising outgoing data frames can subsequently be read out of the FIFO buffer at the second clock rate. In the event the rate at which the digital information is written into the FIFO buffer exceeds a first threshold value, the timing compensation mechanism performs at least one negative justification to allow more space in the outgoing data frames for the information. In the event the rate at which the digital information is read out of the FIFO buffer exceeds a second threshold value, the timing compensation mechanism performs at least one positive justification to allow less space in the outgoing data frames for the information. Such negative and positive justifications are typically performed by removing and inserting, respectively, one or more “stuff” bits from/into the data frames. In this way, data frames can be asynchronously mapped from one clock domain to another.
One drawback of the above-described timing compensation mechanism is that sufficient resolution often cannot be achieved using the FIFO buffer. For example, the FIFO buffer may be configured as a 32×16 byte FIFO buffer to provide a resolution of 16 bytes. This means that when removing or inserting stuff bits from/into the data frames based on whether the rate at which digital information is written into/read out of the FIFO buffer is outside the limits set by the first and second threshold values, the “de-stuffing” and “stuffing” operations would typically have to be performed 16 bytes at a time. However, performing de-stuffing and stuffing operations at such a relatively low byte resolution can unduly complicate the asynchronous mapping of the data frames. In addition, variations in the instantaneous rate of the data frames caused by the interspersing of the stuff bits frequently causes mapping jitter to be introduced into the communications system.
Another approach to implementing the above-described timing compensation mechanism is to employ a circular buffer such as a barrel shifter in place of the FIFO buffer. Like the FIFO buffer, digital information comprising incoming data frames is written into the circular buffer at the first clock rate and subsequently read out of the buffer at the second clock rate. Further, stuffing and de-stuffing operations are performed as needed for asynchronously mapping the data frames from the first clock domain to the second clock domain. Moreover, whereas the exemplary FIFO buffer described above provides 16-byte resolution when performing the stuffing and de-stuffing operations, the circular buffer can be configured to provide an increased resolution of up to 1 byte or higher.
However, the timing compensation mechanism including the circular buffer also has drawbacks. For example, in order to match the size of the above-described 32×16 byte FIFO buffer, the circular buffer would have to be configured to store 512 bytes. Further, a significant amount of control logic would typically be required to control the shifting of the data frame bytes through the 512-byte circular buffer. This can be problematic when implementing the circular buffer on an Application Specific Integrated Circuit (ASIC) because such an implementation would normally entail the use of a relatively large number of custom gates, which can increase the die size and lead to increased manufacturing costs. In addition, like the timing compensation mechanism that includes the FIFO buffer, the mechanism including the circular buffer frequently causes mapping jitter to be introduced into the communications system.
It would therefore be desirable to have a digital communications system that has the capability of asynchronously mapping/de-mapping digital signals from one clock domain to another while reducing the level of mapping jitter introduced into the system. It would also be desirable to have such a digital communications system in which the asynchronous mapping/de-mapping capability can be implemented on one or more ASICs with a reduced number of gates.